The present disclosure relates to semiconductor devices and methods of fabricating the same. More specifically, the present disclosure relates to semiconductor devices utilizing a three-dimensional channel, and methods of fabricating the same.
As a scaling technique to increase the density of semiconductor devices, a multi gate transistor has been proposed in which a silicon body having a fin- or nanowire-shape is formed on a substrate, and gates are formed on the surface of the silicon body.
It may be easy to scale such multi gate transistors since they utilize three-dimensional channels. In addition, it is possible improve current control capability without increasing the gate length of such multi gate transistors. Further, the short-channel effect (SCE) that refers to the influence on the potential at a channel region by a drain voltage can be effectively suppressed.
As semiconductor devices become more integrated, the width of fins or nanowires may be limited. Therefore, adjusting channel implant or source/drain implant may have limited influence on threshold voltages (Vth) of multi gate transistors.